1. Technical Field
This invention relates to electronic circuits, and more particularly, to clocking circuits.
2. Description of the Related Art
Memory interfaces in electronic systems may be arranged to interface with more than one type of memory. For example, a memory interface may be coupled to a storage-type memory, such as flash, and one of various types of random access memory (RAM). In some cases, these memories may be source synchronous. In a source synchronous system, a clock may be sourced with the data provided. Thus, in memory systems that implement source synchronous memories, a clock may be provided when data is returned from the memory during a read.
Since multiple source synchronous memories may be coupled to a memory interface, multiple clock domains may be created. In some cases, these clock signals may be delayed by at least a portion of a cycle for conducting reads to ensure enough set-up and hold time for the incoming data. For multiple clock domains (e.g., from multiple source synchronous clocks from multiple memories), multiple delay locked loops (DLLs) may be implemented to provide the delays. To ensure consistency of the delay time across the clock domains, a DLL for one of the clock domains may be designated as a master DLL, while DLLs for the other clock domains may be designated as slave DLLs. The master DLL may be configured to provide the desired delay to the respective clock signal in its domain. A delay code indicating this delay may be provided to the slave DLLs, which may set their respective delay accordingly.